Various computing devices, such as microprocessors, typically include a plurality of data and address ports that allow the microprocessor to store information in an associated memory at predetermined address locations. In many applications, the memory device will be an electrically eraseable programmable read-only memory (EEPROM). EEPROMs are convenient to use because they can receive and retain information from the microprocessor, and can even retain that information in the absence of power.
Most such memory units include a write enable port that controls when the memory unit can receive and store information. This provides protection against improper data being stored in the memory unit, or disruption of previously stored information. Unfortunately, there do arise circumstances when the write enable port can be incorrectly enabled, thereby allowing the guarded against events to occur. For instance, in automotive applications, various transient events can occur in the power supply lines of an onboard system. Such transient events can sufficiently disrupt system operations to improperly enable the memory unit as described above and thereby derogate the stored information.
In an attempt to avoid such inappropriate writes, some EEPROM manufacturers require that a predetermined data pattern be written to a fixed address prior to enabling memory writes. Another approach has provided a plurality of one shot circuits requiring receipt of a number of clock pulses in a predetermined amount of time before EEPROM writes will be enabled. To date, however, these approaches have either been relatively expensive, or are not compatible with all EEPROM designs. A need therefore exists for an effective, easily implemented, widely compatible memory write protection method and device for such memory units.